OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 9

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4173d 18h /mod_sim_exp/trunk/rtl/vhdl/
8 added descriptive comments JonasDC 4173d 21h /mod_sim_exp/trunk/rtl/vhdl/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4173d 21h /mod_sim_exp/trunk/rtl/vhdl/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4173d 21h /mod_sim_exp/trunk/rtl/vhdl/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4173d 23h /mod_sim_exp/trunk/rtl/vhdl/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4174d 13h /mod_sim_exp/trunk/rtl/vhdl/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4178d 19h /mod_sim_exp/trunk/rtl/vhdl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.