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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 10

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Rev Log message Author Age Path
10 changed signal input port names to correct name JonasDC 3988d 23h /mod_sim_exp/trunk/rtl/vhdl/core/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 3988d 23h /mod_sim_exp/trunk/rtl/vhdl/core/
8 added descriptive comments JonasDC 3989d 01h /mod_sim_exp/trunk/rtl/vhdl/core/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3989d 01h /mod_sim_exp/trunk/rtl/vhdl/core/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3989d 02h /mod_sim_exp/trunk/rtl/vhdl/core/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3989d 04h /mod_sim_exp/trunk/rtl/vhdl/core/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3989d 17h /mod_sim_exp/trunk/rtl/vhdl/core/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3993d 23h /mod_sim_exp/trunk/rtl/vhdl/core/

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