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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 25

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25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4278d 11h /mod_sim_exp/trunk/rtl/vhdl/core/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4281d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
23 added descriptive comments JonasDC 4281d 21h /mod_sim_exp/trunk/rtl/vhdl/core/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4284d 14h /mod_sim_exp/trunk/rtl/vhdl/core/
21 changed x_i signal to xi JonasDC 4285d 22h /mod_sim_exp/trunk/rtl/vhdl/core/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 4285d 22h /mod_sim_exp/trunk/rtl/vhdl/core/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 4290d 17h /mod_sim_exp/trunk/rtl/vhdl/core/
18 updated stages with comments and renamed some signals for consistency JonasDC 4291d 17h /mod_sim_exp/trunk/rtl/vhdl/core/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4291d 22h /mod_sim_exp/trunk/rtl/vhdl/core/
16 package with modified generic parameter for register_n JonasDC 4292d 11h /mod_sim_exp/trunk/rtl/vhdl/core/
15 changed generic for register width from n to width for consistency JonasDC 4292d 11h /mod_sim_exp/trunk/rtl/vhdl/core/
14 changed comments, file is now according to OC design rules JonasDC 4292d 11h /mod_sim_exp/trunk/rtl/vhdl/core/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4292d 12h /mod_sim_exp/trunk/rtl/vhdl/core/
12 updated comments, file is now completely according to design rules JonasDC 4292d 12h /mod_sim_exp/trunk/rtl/vhdl/core/
10 changed signal input port names to correct name JonasDC 4292d 17h /mod_sim_exp/trunk/rtl/vhdl/core/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4292d 17h /mod_sim_exp/trunk/rtl/vhdl/core/
8 added descriptive comments JonasDC 4292d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4292d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4292d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4292d 21h /mod_sim_exp/trunk/rtl/vhdl/core/

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