URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 77

Rev	Log message	Author	Age	Path
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4182d 04h	/mod_sim_exp/trunk/rtl/vhdl/core/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4182d 04h	/mod_sim_exp/trunk/rtl/vhdl/core/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4182d 18h	/mod_sim_exp/trunk/rtl/vhdl/core/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4186d 03h	/mod_sim_exp/trunk/rtl/vhdl/core/
23	added descriptive comments	JonasDC	4186d 05h	/mod_sim_exp/trunk/rtl/vhdl/core/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4188d 22h	/mod_sim_exp/trunk/rtl/vhdl/core/
21	changed x_i signal to xi	JonasDC	4190d 06h	/mod_sim_exp/trunk/rtl/vhdl/core/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4190d 06h	/mod_sim_exp/trunk/rtl/vhdl/core/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4195d 01h	/mod_sim_exp/trunk/rtl/vhdl/core/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4196d 01h	/mod_sim_exp/trunk/rtl/vhdl/core/