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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 90

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90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4045d 15h /mod_sim_exp/trunk/rtl/vhdl/core/
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4109d 13h /mod_sim_exp/trunk/rtl/vhdl/core/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4116d 23h /mod_sim_exp/trunk/rtl/vhdl/core/
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4119d 00h /mod_sim_exp/trunk/rtl/vhdl/core/
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4135d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
75 made rw_address a vector of a fixed width JonasDC 4153d 23h /mod_sim_exp/trunk/rtl/vhdl/core/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4156d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4158d 18h /mod_sim_exp/trunk/rtl/vhdl/core/
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4158d 21h /mod_sim_exp/trunk/rtl/vhdl/core/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4166d 13h /mod_sim_exp/trunk/rtl/vhdl/core/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4166d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4169d 12h /mod_sim_exp/trunk/rtl/vhdl/core/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4169d 12h /mod_sim_exp/trunk/rtl/vhdl/core/
55 updated resource usage in comments JonasDC 4173d 12h /mod_sim_exp/trunk/rtl/vhdl/core/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4173d 12h /mod_sim_exp/trunk/rtl/vhdl/core/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4253d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
43 made the core parameters generics JonasDC 4257d 13h /mod_sim_exp/trunk/rtl/vhdl/core/
41 removed deprecated files from version control JonasDC 4263d 21h /mod_sim_exp/trunk/rtl/vhdl/core/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4272d 12h /mod_sim_exp/trunk/rtl/vhdl/core/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4272d 18h /mod_sim_exp/trunk/rtl/vhdl/core/

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