Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [cell_1b_adder.vhd] - Rev 8


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8 added descriptive comments JonasDC 4283d 07h /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4283d 23h /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4288d 05h /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd

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