URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [counter_sync.vhd] - Rev 77

Rev	Log message	Author	Age	Path
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4172d 20h	/mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4191d 04h	/mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4193d 22h	/mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4198d 04h	/mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd