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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [fifo_primitive.vhd] - Rev 89

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89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 3990d 21h /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4174d 23h /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4179d 04h /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd

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