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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Rev 63

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63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4069d 11h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4156d 12h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
43 made the core parameters generics JonasDC 4160d 05h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
41 removed deprecated files from version control JonasDC 4166d 13h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4175d 04h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4179d 07h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4180d 06h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4180d 15h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4180d 16h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4181d 06h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 4184d 15h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
23 added descriptive comments JonasDC 4184d 16h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4187d 10h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
21 changed x_i signal to xi JonasDC 4188d 17h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4188d 17h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4193d 12h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
18 updated stages with comments and renamed some signals for consistency JonasDC 4194d 12h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4194d 17h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
16 package with modified generic parameter for register_n JonasDC 4195d 06h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names		 JonasDC 4195d 12h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4196d 06h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd

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