URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Rev 84

Rev	Log message	Author	Age	Path
18	updated stages with comments and renamed some signals for consistency	JonasDC	4199d 07h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4199d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
16	package with modified generic parameter for register_n	JonasDC	4200d 01h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4200d 07h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4201d 01h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd