| Rev |
Log message |
Author |
Age |
Path |
| 94 |
BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx |
JonasDC |
4117d 22h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
4123d 21h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 89 |
updated vhdl files so now different clock frequencies are posible for the core and bus interface. |
JonasDC |
4187d 19h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4195d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 75 |
made rw_address a vector of a fixed width |
JonasDC |
4232d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4237d 00h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4244d 19h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4245d 01h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4332d 02h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 43 |
made the core parameters generics |
JonasDC |
4335d 19h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 41 |
removed deprecated files from version control |
JonasDC |
4342d 03h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4350d 18h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4354d 21h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4355d 20h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4356d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4356d 06h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4356d 20h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4360d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 23 |
added descriptive comments |
JonasDC |
4360d 06h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4363d 00h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 21 |
changed x_i signal to xi |
JonasDC |
4364d 07h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4364d 07h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4369d 02h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4370d 02h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4370d 07h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 16 |
package with modified generic parameter for register_n |
JonasDC |
4370d 20h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 9 |
added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names |
JonasDC |
4371d 02h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 3 |
updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation |
JonasDC |
4371d 20h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
