URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [modulus_ram_gen.vhd] - Rev 90

Rev	Log message	Author	Age	Path
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3953d 10h	/mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4017d 08h	/mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4074d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd