URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_dp.vhd] - Rev 89

Rev	Log message	Author	Age	Path
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4018d 07h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4202d 09h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4206d 15h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd