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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_mem.vhd] - Rev 94

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94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 3920d 16h /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3926d 14h /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 3990d 13h /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
75 made rw_address a vector of a fixed width JonasDC 4034d 22h /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4039d 18h /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4047d 18h /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd

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