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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_mem.vhd] - Rev 75

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75 made rw_address a vector of a fixed width JonasDC 4035d 04h /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4040d 00h /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4048d 00h /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd

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