URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_mem.vhd] - Rev 90

Rev	Log message	Author	Age	Path
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3948d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4012d 11h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
75	made rw_address a vector of a fixed width	JonasDC	4056d 21h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4061d 16h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4069d 17h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd