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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_ram.vhd] - Rev 94

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94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 3370d 20h /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3376d 19h /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 3440d 17h /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 3603d 16h /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3624d 18h /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3629d 00h /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd

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