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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_ram_asym.vhd] - Rev 94

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Rev	Log message	Author	Age	Path
94	BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include: - changed RAM and memory to support different clocks - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org) - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers) - added logic for control signals to cross from one clock domain to another - updated testbenches and interfaces accordingly - added log of synthesis of the 2 new fifo's for Xilinx	JonasDC	3942d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3948d 10h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4012d 09h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4038d 16h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4061d 14h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4061d 17h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd

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