URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [operand_ram_asym.vhd] - Rev 77

Rev	Log message	Author	Age	Path
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4061d 06h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4061d 09h	/mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd