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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [register_n.vhd] - Rev 15

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Rev Log message Author Age Path
15 changed generic for register width from n to width for consistency JonasDC 3996d 09h /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3996d 17h /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3997d 10h /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4001d 16h /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd

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