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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [standard_cell_block.vhd] - Rev 37

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17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4173d 15h /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4175d 04h /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4179d 10h /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd

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