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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 40

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Rev Log message Author Age Path
40 adjusted core instantiation to new core module name JonasDC 3733d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3758d 19h /mod_sim_exp/trunk/rtl/vhdl/interface/

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