URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 73

Rev	Log message	Author	Age	Path
73	updated plb interface, mem_style and device generics added	JonasDC	4066d 21h	/mod_sim_exp/trunk/rtl/vhdl/interface/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4075d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4162d 22h	/mod_sim_exp/trunk/rtl/vhdl/interface/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4166d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/
43	made the core parameters generics	JonasDC	4166d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4173d 00h	/mod_sim_exp/trunk/rtl/vhdl/interface/
40	adjusted core instantiation to new core module name	JonasDC	4181d 04h	/mod_sim_exp/trunk/rtl/vhdl/interface/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4206d 23h	/mod_sim_exp/trunk/rtl/vhdl/interface/