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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [axi/] [msec_ipcore_axilite.vhd] - Rev 89

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89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 3991d 13h /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
86 update on previous JonasDC 3997d 15h /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
85 changed so that reset now also affects slave register JonasDC 3997d 15h /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 3999d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4017d 20h /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd

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