URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [axi/] [msec_ipcore_axilite.vhd] - Rev 90

Rev	Log message	Author	Age	Path
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3948d 18h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4012d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
86	update on previous	JonasDC	4018d 18h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
85	changed so that reset now also affects slave register	JonasDC	4018d 18h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4020d 02h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4038d 23h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd