URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [axi/] [msec_ipcore_axilite.vhd] - Rev 91

Rev	Log message	Author	Age	Path
91	changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register.	JonasDC	3953d 03h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3954d 18h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4018d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
86	update on previous	JonasDC	4024d 18h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
85	changed so that reset now also affects slave register	JonasDC	4024d 18h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4026d 02h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4044d 23h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd