OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] - Rev 60

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4134d 20h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4138d 14h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
43 made the core parameters generics JonasDC 4138d 14h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4144d 22h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
40 adjusted core instantiation to new core module name JonasDC 4153d 02h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4178d 21h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.