Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] - Rev 77


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Rev Log message Author Age Path
77 found fault in code, now synthesizes normally JonasDC 3546d 11h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 3551d 18h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
73 updated plb interface, mem_style and device generics added JonasDC 3552d 17h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 3561d 12h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3648d 19h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3652d 12h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
43 made the core parameters generics JonasDC 3652d 12h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3658d 20h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
40 adjusted core instantiation to new core module name JonasDC 3667d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3692d 19h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/

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