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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 52

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Rev Log message Author Age Path
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4354d 04h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
43 made the core parameters generics JonasDC 4357d 22h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4364d 06h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
40 adjusted core instantiation to new core module name JonasDC 4372d 10h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4398d 05h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd

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