Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] - Rev 94


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Rev Log message Author Age Path
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 4029d 18h /mod_sim_exp/trunk/rtl/vhdl/ram/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4035d 17h /mod_sim_exp/trunk/rtl/vhdl/ram/
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4099d 15h /mod_sim_exp/trunk/rtl/vhdl/ram/
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4109d 02h /mod_sim_exp/trunk/rtl/vhdl/ram/
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4148d 23h /mod_sim_exp/trunk/rtl/vhdl/ram/
62 not used anymore JonasDC 4156d 23h /mod_sim_exp/trunk/rtl/vhdl/ram/
61 updated comments, added optional altera constraint JonasDC 4156d 23h /mod_sim_exp/trunk/rtl/vhdl/ram/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4159d 14h /mod_sim_exp/trunk/rtl/vhdl/ram/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4159d 14h /mod_sim_exp/trunk/rtl/vhdl/ram/
53 correctly inferred ram for altera dual port ram JonasDC 4163d 20h /mod_sim_exp/trunk/rtl/vhdl/ram/
52 correct inferring of blockram, no additional resources. JonasDC 4163d 21h /mod_sim_exp/trunk/rtl/vhdl/ram/
51 true dual port ram for xilinx JonasDC 4163d 22h /mod_sim_exp/trunk/rtl/vhdl/ram/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 4163d 22h /mod_sim_exp/trunk/rtl/vhdl/ram/

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