URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] - Rev 53

Rev	Log message	Author	Age	Path
53	correctly inferred ram for altera dual port ram	JonasDC	4827d 01h	/mod_sim_exp/trunk/rtl/vhdl/ram/
52	correct inferring of blockram, no additional resources.	JonasDC	4827d 02h	/mod_sim_exp/trunk/rtl/vhdl/ram/
51	true dual port ram for xilinx	JonasDC	4827d 02h	/mod_sim_exp/trunk/rtl/vhdl/ram/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4827d 02h	/mod_sim_exp/trunk/rtl/vhdl/ram/