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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] - Rev 77

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66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 3615d 10h /mod_sim_exp/trunk/rtl/vhdl/ram/
62 not used anymore JonasDC 3623d 10h /mod_sim_exp/trunk/rtl/vhdl/ram/
61 updated comments, added optional altera constraint JonasDC 3623d 10h /mod_sim_exp/trunk/rtl/vhdl/ram/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 3626d 01h /mod_sim_exp/trunk/rtl/vhdl/ram/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 3626d 01h /mod_sim_exp/trunk/rtl/vhdl/ram/
53 correctly inferred ram for altera dual port ram JonasDC 3630d 07h /mod_sim_exp/trunk/rtl/vhdl/ram/
52 correct inferring of blockram, no additional resources. JonasDC 3630d 08h /mod_sim_exp/trunk/rtl/vhdl/ram/
51 true dual port ram for xilinx JonasDC 3630d 09h /mod_sim_exp/trunk/rtl/vhdl/ram/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3630d 09h /mod_sim_exp/trunk/rtl/vhdl/ram/

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