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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [tdpram_asym.vhd] - Rev 89

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89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4210d 13h /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4259d 22h /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd

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