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[/] [mod_sim_exp/] [trunk/] [sim/] - Rev 102

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101 added README file for simulation, minor update for Makefile clean target. JonasDC 3281d 01h /mod_sim_exp/trunk/sim/
97 changes in makefile, and fifo's are now also in mod_sim_exp library JonasDC 3316d 01h /mod_sim_exp/trunk/sim/
96 minor makefile update JonasDC 3317d 01h /mod_sim_exp/trunk/sim/
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 3329d 21h /mod_sim_exp/trunk/sim/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3335d 20h /mod_sim_exp/trunk/sim/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 3407d 05h /mod_sim_exp/trunk/sim/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 3448d 23h /mod_sim_exp/trunk/sim/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 3456d 19h /mod_sim_exp/trunk/sim/
41 removed deprecated files from version control JonasDC 3554d 02h /mod_sim_exp/trunk/sim/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 3567d 19h /mod_sim_exp/trunk/sim/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 3568d 05h /mod_sim_exp/trunk/sim/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 3568d 05h /mod_sim_exp/trunk/sim/
28 updated makefile for new pipeline sources JonasDC 3568d 19h /mod_sim_exp/trunk/sim/
27 test input values for multiplier_tb JonasDC 3568d 19h /mod_sim_exp/trunk/sim/
24 changed names of top-level module to mod_sim_exp_core JonasDC 3572d 04h /mod_sim_exp/trunk/sim/
11 simulation output folder JonasDC 3582d 22h /mod_sim_exp/trunk/sim/
5 not needed on svn, is generated by testbench JonasDC 3583d 04h /mod_sim_exp/trunk/sim/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3583d 20h /mod_sim_exp/trunk/sim/

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