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[/] [mod_sim_exp/] [trunk/] [sim/] - Rev 92

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Rev Log message Author Age Path
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3381d 21h /mod_sim_exp/trunk/sim/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 3453d 05h /mod_sim_exp/trunk/sim/
70 updated testbench for use with new core parameters
updated makefile, added new sources		 JonasDC 3495d 00h /mod_sim_exp/trunk/sim/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 3502d 19h /mod_sim_exp/trunk/sim/
41 removed deprecated files from version control JonasDC 3600d 03h /mod_sim_exp/trunk/sim/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 3613d 19h /mod_sim_exp/trunk/sim/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 3614d 05h /mod_sim_exp/trunk/sim/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 3614d 05h /mod_sim_exp/trunk/sim/
28 updated makefile for new pipeline sources JonasDC 3614d 19h /mod_sim_exp/trunk/sim/
27 test input values for multiplier_tb JonasDC 3614d 19h /mod_sim_exp/trunk/sim/
24 changed names of top-level module to mod_sim_exp_core JonasDC 3618d 04h /mod_sim_exp/trunk/sim/
11 simulation output folder JonasDC 3628d 23h /mod_sim_exp/trunk/sim/
5 not needed on svn, is generated by testbench JonasDC 3629d 04h /mod_sim_exp/trunk/sim/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 3629d 20h /mod_sim_exp/trunk/sim/

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