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[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Rev 27

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Rev Log message Author Age Path
24 changed names of top-level module to mod_sim_exp_core JonasDC 4163d 01h /mod_sim_exp/trunk/sim/Makefile
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4174d 16h /mod_sim_exp/trunk/sim/Makefile

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