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[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Rev 36

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31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4159d 18h /mod_sim_exp/trunk/sim/Makefile
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4159d 19h /mod_sim_exp/trunk/sim/Makefile
28 updated makefile for new pipeline sources JonasDC 4160d 09h /mod_sim_exp/trunk/sim/Makefile
24 changed names of top-level module to mod_sim_exp_core JonasDC 4163d 18h /mod_sim_exp/trunk/sim/Makefile
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4175d 09h /mod_sim_exp/trunk/sim/Makefile

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