Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim] - Rev 101


Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
101 added README file for simulation, minor update for Makefile clean target. JonasDC 3389d 06h /mod_sim_exp/trunk/sim
97 changes in makefile, and fifo's are now also in mod_sim_exp library JonasDC 3424d 06h /mod_sim_exp/trunk/sim
96 minor makefile update JonasDC 3425d 06h /mod_sim_exp/trunk/sim
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 3438d 02h /mod_sim_exp/trunk/sim
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3444d 01h /mod_sim_exp/trunk/sim
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 3515d 10h /mod_sim_exp/trunk/sim
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 3557d 04h /mod_sim_exp/trunk/sim
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 3565d 00h /mod_sim_exp/trunk/sim
41 removed deprecated files from version control JonasDC 3662d 07h /mod_sim_exp/trunk/sim
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 3676d 00h /mod_sim_exp/trunk/sim
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 3676d 10h /mod_sim_exp/trunk/sim
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 3676d 10h /mod_sim_exp/trunk/sim
28 updated makefile for new pipeline sources JonasDC 3677d 00h /mod_sim_exp/trunk/sim
27 test input values for multiplier_tb JonasDC 3677d 00h /mod_sim_exp/trunk/sim
24 changed names of top-level module to mod_sim_exp_core JonasDC 3680d 09h /mod_sim_exp/trunk/sim
11 simulation output folder JonasDC 3691d 03h /mod_sim_exp/trunk/sim
5 not needed on svn, is generated by testbench JonasDC 3691d 09h /mod_sim_exp/trunk/sim
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3692d 01h /mod_sim_exp/trunk/sim

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.