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[/] [mod_sim_exp/] [trunk] - Rev 12

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Rev Log message Author Age Path
12 updated comments, file is now completely according to design rules JonasDC 4195d 08h /mod_sim_exp/trunk
11 simulation output folder JonasDC 4195d 10h /mod_sim_exp/trunk
10 changed signal input port names to correct name JonasDC 4195d 13h /mod_sim_exp/trunk
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names		 JonasDC 4195d 13h /mod_sim_exp/trunk
8 added descriptive comments JonasDC 4195d 15h /mod_sim_exp/trunk
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4195d 15h /mod_sim_exp/trunk
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4195d 16h /mod_sim_exp/trunk
5 not needed on svn, is generated by testbench JonasDC 4195d 16h /mod_sim_exp/trunk
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4195d 17h /mod_sim_exp/trunk
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4196d 07h /mod_sim_exp/trunk
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4200d 13h /mod_sim_exp/trunk
1 The project and the structure was created root 4202d 13h /mod_sim_exp/trunk

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