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Rev	Log message	Author	Age	Path
103	Updated documentation to version 1.5 with dual-clock support	JonasDC	3890d 10h	/
102	Added some extra information for the test generation software	JonasDC	3890d 10h	/
101	added README file for simulation, minor update for Makefile clean target.	JonasDC	3890d 15h	/
100	added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. previous tag was incorrect, now updated	JonasDC	3908d 22h	/
99	removed tag, wrong directory tagged	JonasDC	3908d 22h	/
98	added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up.	JonasDC	3908d 22h	/
97	changes in makefile, and fifo's are now also in mod_sim_exp library	JonasDC	3925d 15h	/
96	minor makefile update	JonasDC	3926d 15h	/
95	new control logic for the core, allow for greater frequencies for the multiplier. changes: - autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure. - mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.	JonasDC	3926d 15h	/
94	BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include: - changed RAM and memory to support different clocks - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org) - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers) - added logic for control signals to cross from one clock domain to another - updated testbenches and interfaces accordingly - added log of synthesis of the 2 new fifo's for Xilinx	JonasDC	3939d 11h	/
93	Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface.	JonasDC	3941d 17h	/
92	updated documentation with minor interrupt changes of AXI interface	JonasDC	3941d 17h	/
91	changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register.	JonasDC	3943d 20h	/
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3945d 10h	/
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4009d 08h	/
88	small update on documentation, changed fault in axi control_reg	JonasDC	4015d 09h	/
87	updated documentation to version 1.4 core now supports the AXI4-Lite bus	JonasDC	4015d 10h	/
86	update on previous	JonasDC	4015d 10h	/
85	changed so that reset now also affects slave register	JonasDC	4015d 10h	/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4016d 19h	/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4018d 19h	/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4035d 15h	/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4035d 16h	/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4045d 09h	/
79	Tag for version 1.3 (with new ram style	JonasDC	4045d 09h	/
78	updated documentation with new RAM style information	JonasDC	4045d 09h	/
77	found fault in code, now synthesizes normally	JonasDC	4051d 07h	/
76	testbench update	JonasDC	4053d 18h	/
75	made rw_address a vector of a fixed width	JonasDC	4053d 18h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4056d 14h	/

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