URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 45

Rev	Log message	Author	Age	Path
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4186d 20h	/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4190d 05h	/
23	added descriptive comments	JonasDC	4190d 06h	/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4193d 00h	/
21	changed x_i signal to xi	JonasDC	4194d 08h	/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4194d 08h	/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4199d 03h	/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4200d 02h	/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4200d 07h	/
16	package with modified generic parameter for register_n	JonasDC	4200d 21h	/