Rev |
Log message |
Author |
Age |
Path |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4162d 03h |
/ |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4162d 03h |
/ |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4165d 20h |
/ |
43 |
made the core parameters generics |
JonasDC |
4165d 20h |
/ |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4172d 04h |
/ |
41 |
removed deprecated files from version control |
JonasDC |
4172d 04h |
/ |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4180d 08h |
/ |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4180d 19h |
/ |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4181d 01h |
/ |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4184d 22h |
/ |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4185d 18h |
/ |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4185d 20h |
/ |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4185d 22h |
/ |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4186d 00h |
/ |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4186d 01h |
/ |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4186d 07h |
/ |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4186d 07h |
/ |
29 |
added software for generation of test input for the tesbenches |
JonasDC |
4186d 20h |
/ |
28 |
updated makefile for new pipeline sources |
JonasDC |
4186d 21h |
/ |
27 |
test input values for multiplier_tb |
JonasDC |
4186d 21h |
/ |
26 |
testbench for only the montgommery multiplier |
JonasDC |
4186d 21h |
/ |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4186d 21h |
/ |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4190d 06h |
/ |
23 |
added descriptive comments |
JonasDC |
4190d 07h |
/ |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4193d 01h |
/ |
21 |
changed x_i signal to xi |
JonasDC |
4194d 08h |
/ |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4194d 09h |
/ |
19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4199d 04h |
/ |
18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4200d 03h |
/ |
17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4200d 08h |
/ |