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Rev Log message Author Age Path
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 3636d 05h /
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 3636d 05h /
58 made fifo full a warning JonasDC 3639d 06h /
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 3639d 06h /
56 this is a branch to test performance of a new style of ram JonasDC 3639d 08h /
55 updated resource usage in comments JonasDC 3640d 05h /
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 3640d 05h /
53 correctly inferred ram for altera dual port ram JonasDC 3640d 12h /
52 correct inferring of blockram, no additional resources. JonasDC 3640d 12h /
51 true dual port ram for xilinx JonasDC 3640d 13h /
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3640d 13h /
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 3652d 08h /
48 Tag of the starting version of the project JonasDC 3652d 08h /
47 added documentation for the IP core. JonasDC 3720d 13h /
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3720d 13h /
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3720d 13h /
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3724d 06h /
43 made the core parameters generics JonasDC 3724d 06h /
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3730d 14h /
41 removed deprecated files from version control JonasDC 3730d 14h /

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