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Rev Log message Author Age Path
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4040d 06h /
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4047d 21h /
64 added synthesis reports of xilinx and altera JonasDC 4048d 03h /
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4048d 03h /
62 not used anymore JonasDC 4048d 06h /
61 updated comments, added optional altera constraint JonasDC 4048d 06h /
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4050d 20h /
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4050d 20h /
58 made fifo full a warning JonasDC 4053d 21h /
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 4053d 21h /
56 this is a branch to test performance of a new style of ram JonasDC 4053d 23h /
55 updated resource usage in comments JonasDC 4054d 20h /
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4054d 20h /
53 correctly inferred ram for altera dual port ram JonasDC 4055d 03h /
52 correct inferring of blockram, no additional resources. JonasDC 4055d 03h /
51 true dual port ram for xilinx JonasDC 4055d 04h /
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 4055d 04h /
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4066d 23h /
48 Tag of the starting version of the project JonasDC 4066d 23h /
47 added documentation for the IP core. JonasDC 4135d 04h /
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4135d 04h /
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4135d 04h /
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4138d 21h /
43 made the core parameters generics JonasDC 4138d 21h /
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4145d 05h /
41 removed deprecated files from version control JonasDC 4145d 05h /
40 adjusted core instantiation to new core module name JonasDC 4153d 09h /
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4153d 20h /
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4154d 02h /
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4157d 23h /

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