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Rev Log message Author Age Path
19 Fixed r/w trigger in direct operations pradd 2849d 00h /
18 Fixed r/w trigger in direct operations pradd 2849d 00h /
17 Fixed documentation pradd 2849d 10h /
16 Added bypass commands to the controller's interface pradd 2849d 10h /
15 Added Avalon Memory Mapped slave interface pradd 3134d 11h /
14 Fixed READ_PAGE initial delay bug. Now the first byte is the first byte, not 0 :-) pradd 3134d 11h /
13 Fixed delay handling in M_NAND_READ_PARAM_PAGE pradd 3135d 08h /
12 Minor changes to nand_master.vhd and onfi_package.vhd.
Added documentation.		 pradd 3154d 09h /
11 Changed io_unit data_reg assignment timing.

Added testbench.vhd.		 pradd 3157d 12h /
10 Minor fixes. pradd 3158d 07h /
9 Submission of actually working code :-) pradd 3158d 15h /
8 Initial check in of nand_ctrl.vhd - this file implements the "system side" interface of the NAND
flash controller.		 pradd 3247d 10h /
7 Added a note on clock_cycle generic signal pradd 3247d 13h /
6 Initial check in of 'NAND_STUFF' package. pradd 3248d 08h /
5 Added physical connection table for 'nand_io' bits/pins pradd 3248d 09h /
4 Added some explanation regarding x8 and x16 NAND devices pinout and the way
data input/output is organized in the module.		 pradd 3248d 09h /
3 Added CE2# - Chip Enable for second die on 8Gbit x8 devices
Added is_x16 input - indicates whether the NAND being used is x8 or x16 device
Added die_select input - selects active die (on 8GBit devices only)

Fixed nand_io[15..0] pin mux to properly support x16 devices		 pradd 3248d 09h /
2 Initial check-in:
nand_interface.vhd - contains implementation of simplistic NAND Flash interface. Although,
the module may be used as a standalone "controller", it is suggested to use the whole package.		 pradd 3248d 13h /
1 The project and the structure was created root 3249d 00h /

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