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Rev Log message Author Age Path
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1876d 03h /
181 Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. jshamlet 1877d 00h /
180 Added additional Open8 compatible modules jshamlet 1881d 03h /
179 Replacing files accidentally deleted during check-in jshamlet 1890d 23h /
178 Adding Open8 toolset for pure assembly jshamlet 1891d 00h /
177 Fixed comments in RTC module jshamlet 3201d 04h /
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.		 jshamlet 3206d 01h /
175 Added 4 and 8-bit LCD interfaces with backlight and contrast DACs jshamlet 3206d 06h /
174 Added ROM/RAM wrappers jshamlet 3401d 01h /
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3401d 01h /
172 General code cleanup jshamlet 3401d 01h /
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3401d 01h /
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3401d 01h /
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3456d 02h /
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 4234d 22h /
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 4242d 21h /
166 fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301 khays 4806d 22h /
165 fixed issues with PC relative fixups in the linker khays 4808d 05h /
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4878d 16h /
163 sync with binutils 2.22.51.20111114 khays 4916d 04h /

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