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[/] [open8_urisc/] - Rev 166

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166 fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301 khays 4765d 08h /open8_urisc/
165 fixed issues with PC relative fixups in the linker khays 4766d 15h /open8_urisc/
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4837d 03h /open8_urisc/
163 sync with binutils 2.22.51.20111114 khays 4874d 14h /open8_urisc/
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4927d 20h /open8_urisc/
161 synchronize binutils/ with gnu dev tree of 2.21.53.20110828 khays 4951d 14h /open8_urisc/
160 synchronize binutils/gas with gnu dev tree of 2.21.53.20110828 khays 4951d 14h /open8_urisc/
159 synchronize binutils/gold with gnu dev tree of 2.21.53.20110828 khays 4951d 14h /open8_urisc/
158 synchronize binutils/opcodes with gnu dev tree of 2.21.53.20110828 khays 4951d 14h /open8_urisc/
157 synchronize binutils/ld with gnu dev tree of 2.21.53.20110828 khays 4951d 14h /open8_urisc/
156 Optimized for timing,
Flattened block structure to single entity.		 jshamlet 4984d 10h /open8_urisc/
155 Fixed additional interrupt logic bug,
Optimized several blocks - including ALU, stack, program counter, and data path.		 jshamlet 4985d 05h /open8_urisc/
154 Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed. jshamlet 4990d 08h /open8_urisc/
153 Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.		 jshamlet 5017d 03h /open8_urisc/
152 Correct the descriptions for GMSK and SMSK instructions in the Open8 Assembly Language Reference khays 5025d 06h /open8_urisc/
151 Fixed STO instruction and interrupt logic to avoid address bus corruption issues. jshamlet 5027d 06h /open8_urisc/
150 Updated the assembly language reference to add the CLR pseudo-mnemonic khays 5027d 14h /open8_urisc/
149 added clr "Clear Accumulator" pseudo-instruction khays 5027d 16h /open8_urisc/
148 catch up with binutils trunk through date-version 20110613 khays 5028d 10h /open8_urisc/
147 GNU binutils port for Open8 - addition of all remaining files khays 5037d 04h /open8_urisc/

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