| Rev |
Log message |
Author |
Age |
Path |
| 216 |
Fixed missing parenthesis |
jshamlet |
1913d 01h |
/open8_urisc/ |
| 215 |
More code cleanup |
jshamlet |
1913d 01h |
/open8_urisc/ |
| 214 |
Initial add of some older code |
jshamlet |
1916d 23h |
/open8_urisc/ |
| 213 |
Code and comment cleanup |
jshamlet |
1917d 00h |
/open8_urisc/ |
| 212 |
Fixed issue with rewritten epoch timer not clearing alarm on set point write. |
jshamlet |
1917d 06h |
/open8_urisc/ |
| 211 |
Ok, this time with feeling. Timer should now properly reset on interval update. |
jshamlet |
1918d 04h |
/open8_urisc/ |
| 210 |
Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes. |
jshamlet |
1918d 06h |
/open8_urisc/ |
| 209 |
Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core. |
jshamlet |
1918d 19h |
/open8_urisc/ |
| 208 |
Removed unnecessary package references |
jshamlet |
1919d 04h |
/open8_urisc/ |
| 207 |
Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. |
jshamlet |
1919d 21h |
/open8_urisc/ |
| 206 |
Merged interrupt logic with other clocked process. |
jshamlet |
1923d 16h |
/open8_urisc/ |
| 205 |
More code and comment cleanup for the new SDLC engine |
jshamlet |
1923d 16h |
/open8_urisc/ |
| 204 |
Fixed more incorrect comments |
jshamlet |
1923d 17h |
/open8_urisc/ |
| 203 |
Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. |
jshamlet |
1923d 23h |
/open8_urisc/ |
| 202 |
Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier. |
jshamlet |
1923d 23h |
/open8_urisc/ |
| 201 |
Fixed comments regarding RX Checksum location |
jshamlet |
1925d 21h |
/open8_urisc/ |
| 200 |
Renamed dual-port buffer to match other entities. |
jshamlet |
1925d 21h |
/open8_urisc/ |
| 199 |
Added monitor ram for debugging and fixed issue with dual-port read path. |
jshamlet |
1925d 21h |
/open8_urisc/ |
| 198 |
Removed debugging memory |
jshamlet |
1926d 05h |
/open8_urisc/ |
| 197 |
Fixed incorrect comments |
jshamlet |
1926d 05h |
/open8_urisc/ |
| 196 |
Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) |
jshamlet |
1926d 06h |
/open8_urisc/ |
| 195 |
Added dual-port RAM core for SDLC interface. |
jshamlet |
1927d 01h |
/open8_urisc/ |
| 194 |
Cleaned up licensing sections |
jshamlet |
1927d 01h |
/open8_urisc/ |
| 193 |
Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation. |
jshamlet |
1927d 01h |
/open8_urisc/ |
| 192 |
Added SDLC packet engine |
jshamlet |
1927d 01h |
/open8_urisc/ |
| 191 |
Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it. |
jshamlet |
1927d 01h |
/open8_urisc/ |
| 190 |
Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00. |
jshamlet |
1938d 23h |
/open8_urisc/ |
| 189 |
Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals. |
jshamlet |
1940d 00h |
/open8_urisc/ |
| 188 |
Added a generic to alter the behavior of RTI so that it can optionally skip restoring the general purpose flags GP4 to GP7, allowing ISR's to make persistent changes to them. Also exported these flags to the top level for use outside the CPU. |
jshamlet |
1940d 02h |
/open8_urisc/ |
| 187 |
Added the CPU_Halt input, only now as an input to the instruction decoder. The CPU_Halt line will assert the registered CPU_Halt_Req, which will cause the instruction decoder to abort the current instruction, reset the PC, then enter a hold state until the line is deasserted. Additionally, a very minor bug that could cause the SMSK instruction to effectively execute twice if interrupted was fixed. Lastly, cleaned up the comments even more. |
jshamlet |
1941d 23h |
/open8_urisc/ |
