OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] - Rev 295

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
295 Undoing previous revision. UART was fine, bug reporter was not. jshamlet 1154d 06h /open8_urisc/
294 Fixed an ancient bug in the parity logic that had the parity inverted. jshamlet 1154d 11h /open8_urisc/
293 Fixed formatting issue in o8_sync_serial where tabs were inserted instead of spaces and fixed column spacing as a result (purely cosmetic) jshamlet 1173d 11h /open8_urisc/
292 Updated the o8_trig_delay entity by:
1) Added a global interrupt enable,
2) Added the ability to trigger on both the pre- and post-arm trigger input
3) Added the ability to read the external input on offset 7
jshamlet 1244d 10h /open8_urisc/
291 Added Notepad++ language definition file for the Open8_II ISA jshamlet 1287d 00h /open8_urisc/
290 Added an additional generic "Rotation_Ignores_Carry" that removes the carry logic from the ROL/ROR instructions such that they now rotate 'normally',
Added an alias for PSR_GP4 named PSR_S, as it is now used to switch the function of the RSP instruction. The internal opcode hasn't changed, but it allows assembly code to use PSR_S or BRS/BNS when performing RSP related operations.
jshamlet 1287d 00h /open8_urisc/
289 Added back the delay for the cursor home command, since it is slow on most Hitachi compatible LCD panels. jshamlet 1304d 11h /open8_urisc/
288 Removed hard-wired R/Wn output and replaced it with a note that the R/Wn line must be tied low either in firmware or on the board. jshamlet 1305d 07h /open8_urisc/
287 Fixed mangled comments and revisioning dates. jshamlet 1306d 06h /open8_urisc/
286 Added initial cut of a "universal" character LCD driver. Allows for adjustment of address setup, enable high, and cycle times. Also has built-in timers for handling timing on certain commands. jshamlet 1306d 07h /open8_urisc/
285 Added checksum byte to vector tx/rx to avoid issues with serial line noise glitching the receiver. Also modified the transmitted to take any generic argument, rather than canned arguments. jshamlet 1313d 10h /open8_urisc/
284 Corrected the vhdl unit name and description for o8_7seg.vhd jshamlet 1426d 21h /open8_urisc/
283 Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop. jshamlet 1430d 08h /open8_urisc/
282 Modified the SDLC core transmit states to have consistent naming. jshamlet 1430d 09h /open8_urisc/
281 Added pre-initialization to the dual-port RAM signals. jshamlet 1430d 12h /open8_urisc/
280 Got rid of silly aliases that connected the dual-port memory and the arbitration logic. jshamlet 1430d 12h /open8_urisc/
279 More comment cleanup jshamlet 1431d 09h /open8_urisc/
278 Flattened the SDLC interface to fewer files and eliminated the package file. jshamlet 1432d 03h /open8_urisc/
277 Fixed documentation errors related to flags. The UPP ALU instruction only alters the C flag, not the Z or N flags. This implies that using indexed loads or stores with auto post-increment will potentially alter the C flag. jshamlet 1432d 09h /open8_urisc/
276 More comment fixes jshamlet 1467d 06h /open8_urisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.