| Rev |
Log message |
Author |
Age |
Path |
| 242 |
Added write protect logic to the RAM cores and system timer as part of scheme to keep tasks from messing up the scheduler or other task's memory. The RAM is now divided into regions with a separate write mask register. The write mask register itself is only writeable with the I bit is set (during an interrupt or by setting it using STP PSR_I). The 1K memory is divided into 16, 64 byte regions while the 4K memory is divided into 32, 128 byte regions. The system timer simply checks for the I bit being set when the write protect generic is set.
Note that setting the write_protect generic false, or leaving it unset, will keep the previous behavior. |
jshamlet |
1709d 14h |
/open8_urisc/trunk/ |
| 241 |
Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation. |
jshamlet |
1714d 09h |
/open8_urisc/trunk/ |
| 240 |
Simplified the vector tx/rx system to a single line. An idle detector replaces the attn_req signal. |
jshamlet |
1716d 13h |
/open8_urisc/trunk/ |
| 239 |
More cleanup and notation of board to board I/O |
jshamlet |
1716d 18h |
/open8_urisc/trunk/ |
| 238 |
Removed extraneous reference to Ints.VEC_Flag from task.s, since it is supposed to be in the init function in test_fn.s. |
jshamlet |
1717d 13h |
/open8_urisc/trunk/ |
| 237 |
Found some errors in the comments and cleaned up unnecessary library references. |
jshamlet |
1717d 16h |
/open8_urisc/trunk/ |
| 236 |
More software cleanup for the Open8_II project |
jshamlet |
1717d 16h |
/open8_urisc/trunk/ |
| 235 |
Ok, this time with feeling. |
jshamlet |
1722d 11h |
/open8_urisc/trunk/ |
| 234 |
Forgot to add documentation |
jshamlet |
1722d 13h |
/open8_urisc/trunk/ |
| 233 |
Updated the Sample Projects.zip |
jshamlet |
1722d 13h |
/open8_urisc/trunk/ |
| 232 |
More code cleanup on sample projects. SDLC2LCD should now match the Open8_II project model. |
jshamlet |
1731d 17h |
/open8_urisc/trunk/ |
| 231 |
Updated sample projects and added elapsed time capture (chronometer) module |
jshamlet |
1731d 17h |
/open8_urisc/trunk/ |
| 230 |
Added two sample projects that show how to connect and program an Open8 system |
jshamlet |
1735d 04h |
/open8_urisc/trunk/ |
| 229 |
Created a new version of the system timer with 24-bit, 1-uS resolution. The new timer has a much different register interface, so it is now o8_sys_timer_ii. |
jshamlet |
1735d 14h |
/open8_urisc/trunk/ |
| 228 |
Added an initialization constant for the OPEN8_BUS_TYPE record. |
jshamlet |
1736d 04h |
/open8_urisc/trunk/ |
| 227 |
Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses. |
jshamlet |
1736d 11h |
/open8_urisc/trunk/ |
| 226 |
Forgot the updated package file... |
jshamlet |
1736d 15h |
/open8_urisc/trunk/ |
| 225 |
Added Halt_Ack to go with Halt_Req. |
jshamlet |
1736d 15h |
/open8_urisc/trunk/ |
| 224 |
Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. |
jshamlet |
1736d 17h |
/open8_urisc/trunk/ |
| 223 |
Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. |
jshamlet |
1737d 10h |
/open8_urisc/trunk/ |
